Minutes, IBIS Quality Committee 14 Apr 2015 11:00-12:00 EST (08:00-09:00 PST) ROLL CALL eASIC: David Banas Ericsson: Anders Ekholm Intel: Michael Mirmak Eugene Lim IO Methodology Lance Wang Signal Integrity Software * Mike LaBonte Teraspeed Labs: * Bob Ross Everyone in attendance marked by * NOTE: "AR" = Action Required. -----------------------MINUTES --------------------------- Mike LaBonte conducted the meeting. Call for IBIS related patent disclosures: - None Call for opens: ARs: - Mike recover percent format specifications in spreadsheet. - No new progress. - Mike add comments to CMerged Pinsin NumbersT, DLY, MSPEC sections. - No new progress. - Lance add comments to EBD section. - No new progress. - Bob add comments to CIRCUIT section. - No new progress. Parser development: - Bob showed the latest parser contract and described the changes. - Bob showed information derived from BIRD175. - Bob: We have to describe this carefully to Atul. - BIRD175 creates different rules for power and ground pins. - Before this we made no distinction. - For signal pins the new rules don't apply. - Mike: This is checked after everything has has been parsed? - Bob: Yes. This is what the EDA tool should do. - These tables show the expected package model sources. - Circuit_Call can not be used with [Pin Mapping]. - [Merged Pins] requires [Pin Mapping]. - Therefore Circuit_Call can not be used with [Merged Pins]. - There are tables for signal pins, power, ground, etc. - Mike: This might become background for BIRD175. - Bob: All pins of a [Pin Mapping] bus must be in [Pin Numbers] or [Merged Pins]. - But if no [Pin Numbers] at all it falls through to RLC. - This rule might be debated. - A .pkg file might be checked separately from the .ibs file. - In that case some but not all checks can be done. - In the context of a [Component] [Pin Mapping] might exist. - Mike: We should define which checks are Errors and Warnings. - Bob: They are all Errors. Meeting ended: 12:21 Next meeting April 21